Clock signals are often used in electronic circuits for timing internal operation of various circuits necessary to execute an operation. For example, in synchronous memories, external clock signals are provided to the memory and internally distributed to different circuits of the circuit to carry out memory operations.
FIG. 1 illustrates a clock generator circuit 100 that includes a delay-locked loop (DLL) and duty-cycle correction (DCC) circuit. The DLL provides (e.g. generates) an output clock signal that is in phase with a reference input clock signal. The DCC circuit corrects a duty cycle distortion (i.e., duty cycle other than 50%) of the clock signal. The clock generator circuit 100 includes an input buffer circuit 104 that receives an input clock signal and buffers the same to provide a buffered input clock signal to a coarse delay line circuit 108. The delay of the coarse delay line circuit 108 can be adjusted to add delay to the buffered input clock signal. A fine delay line circuit 112 receives the coarsely delayed clock signal and can be adjusted to add finer delay. The coarsely and finely delayed clock signal is then provided to a DCC adjustment circuit 116 that alters the duty cycle of the clock signal to provide a duty cycle corrected clock signal. A static tOH trim circuit 120 coupled to the DCC adjustment circuit 116 provides tOH trim (i.e., to trim static duty cycle of the clock signal) to provide a tOH trimmed clock signal that is driven by a clock driver circuit 124 to provide an output clock signal.
The output clock signal is provided to a clock divider circuit 218 to provide a divided clock signal having a lower clock frequency than the output clock signal. A delay model 132 is coupled to receive the trimmed clock signal and add a model delay representing propagation delays between the input and output of the clock generator 100. A phase detector detects a phase difference between the model delayed clock signal and the output of the input buffer circuit 104. In response a phase difference signal is provided to a delay line control circuit 138, which provides delay control signals to set the adjustable delay of the coarse and fine delay lines 108, 112 to reduce the detected phase difference. The phase difference is reduced until the model delay clock signal and the buffered input clock signal are in phase.
A forward clock path of the clock generator circuit 100 includes the input buffer circuit 104, coarse and fine delay line circuits 108, 112, the clock driver circuit 124, the DCC adjustment circuit 116, the static tOH trim circuit 120 and the a clock driver circuit 124. Each of these circuits include transistor circuitry which introduce propagation delay to the clock signal, are susceptible to varying performance due to variations in operating and process conditions, and decrease responsiveness of the output clock signal to changes in coarse and fine delay. For example, the DCC adjustment circuit 116 may have 12 gates (i.e. transistors) when it is enabled to correct duty-cycle error, the static tOH trim circuit 120 may have 4 gates, and the clock driver circuit 124 may have 2 gates. A total of 18 gates are added after the fine delay line 112 to the forward path. Where clock stability and/or responsive performance are desired, a clock generator circuit presenting these problems in the forward clock path may be undesirable.